1. Field of the Invention
The present invention relates to a laminated ceramic capacitor, and more particularly, to a laminated ceramic capacitor which includes a dielectric ceramic layer containing a barium titanate based compound as its main constituent and includes an internal electrode containing Ni as its main constituent.
2. Description of the Related Art
Conventionally, barium titanate based compounds with high dielectric constants have been used as ceramic materials for laminated ceramic capacitors, and inexpensive Ni which has a favorable conductivity has been widely used as an internal electrode material.
Furthermore, a reduction in size and increase in capacitance for laminated ceramic capacitors have been progressed rapidly with the developments in electronics technology in recent years.
This type of laminated ceramic capacitor has dielectric ceramic layers and internal electrodes which are stacked alternately, and has external electrodes formed on both ends of a ceramic sintered body obtained by a firing treatment. The dielectric ceramic layers are reduced in layer thickness and a larger number of layers stacked, thereby allowing for a reduction in size and an increase in capacitance for the laminated ceramic capacitors.
Japanese Unexamined Patent Publication No. 2002-270458 (claim 1, paragraphs 0031, 0033 and 0056) proposes a laminated ceramic capacitor in which dielectric ceramic layers have a defective area ratio of 1% or less at a polished surface in cross section, and interface layers containing a constituent of the dielectric ceramic layers and a constituent of internal electrodes are formed between the dielectric ceramic layers and the internal electrodes.
Japanese Unexamined Patent Publication No. 2002-270458 (claim 1, paragraphs 0031, 0033 and 0056) discloses a laminated ceramic capacitor which has dielectric ceramic layers containing at least Ba, Ti, Si, and Mg, internal electrodes containing at least Si, and interface layers containing an oxide of Ba—Ti—Si—Mg as their main constituent.
In the case of Japanese Unexamined Patent Publication No. 2002-270458 (claim 1, paragraphs 0031, 0033 and 0056), the dielectric ceramic layers are formed to have a defective area ratio of 1% or less at a polished surface in cross section thereof, in order for the dielectric ceramic layers to have a dense structure, and in addition, the formation of the interface layers provides stronger joining between the dielectric ceramic layers and the internal electrodes. Furthermore, the dielectric ceramic layers, the internal electrodes, and the interface layers contain the constituent elements mentioned above, thereby providing favorable thermal shock resistance, high temperature load characteristics, and dielectric characteristics in the case of a laminated ceramic capacitor with the dielectric ceramic layers being 3 μm in thickness and a number of stacked layers on the order of 150.